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Clocking frequencies continue to increase due to the demand for higher performance. Together with the larger die sizes, multiple clock cycles are now required to cross a chip. A routing tool must thus insert registers as well as buffers while minimizing the path latency. This paper addresses optimal buffered path construction across multiple clock cycles using 2-phase transparent latches. We demonstrate the benefits of routing using latches over registers, and we present a polynomial routing algorithm. Our results confirm the correctness of our algorithm.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:4 )
Date of Conference: 25-28 May 2003