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5 GHz pipelined multiplier and MAC in 0.18 μm complementary static CMOS

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2 Author(s)
Sulistyo, J. ; Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA ; Ha, D.

Wave pipelining improves the throughput of a circuit by exploiting the delays of combinational elements, rather than register clocks, for synchronization. Our proposed approach, called HyPipe, combines conventional pipelining with wave pipelining and aims to take advantage of both pipelining methods. In this paper, we investigated 4-bit signed multipliers and 4-bit MACs based on the HyPipe approach. The circuits were implemented in fully complementary CMOS in TSMC 0.18 μm technology. Simulation results indicate that the two circuits can operate at 5 GHz at 1.8 V and 1.05 GHz at 0.8 V, which are far higher than previous results reported in the open literature.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003