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Variable delay ripple carry adder with carry chain interrupt detection

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4 Author(s)
A. Burg ; Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland ; F. K. Girkaynak ; H. Kaeslin ; W. Fichtner

A statistical approach for the area efficient implementation of fast wide operand adders using early termination detection is described and analyzed. It is shown that high throughput can be achieved based on area- and routing-efficient ripple-carry adders with only marginal overhead. They share a low AT-product with Brent-Kung adders but provide designers with totally different area/delay tradeoffs. The circuit does not require full-custom design and fits well into both self-timed and synchronous designs.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003