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Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit

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2 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chia-Sheng Tsai

This paper presents a 2.5 V/5 V mixed-voltage CMOS I/O buffer that does not need a CMOS technology with a dual-oxide option and complex bias circuits. The proposed mixed-voltage I/O buffer with simpler circuit structure can overcome the problems of leakage current and gate-oxide reliability, which occurring in the conventional CMOS I/O buffer. In this work, the new proposed design has been realized in a 0.25 μm CMOS process, but it can be easily scaled toward 0.18 μm or 0.15 μm processes to serve a 1.8 V/3.3 V mixed-voltage I/O interface.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003