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A CMOS charge pump for sub-2.0 V operation

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3 Author(s)
Kuo-Hsing Cheng ; Dept. of Electr. Eng., Tamkang Univ., Taiwan ; Chung-Yu Chang ; Chia-Hung Wei

A new charge pump circuit is proposed in this paper. The major factors that will limit the charge pump gain and efficiency are threshold voltage drop and body effect. In this paper, the proposed positive charge pump circuit uses the charge transfer switches and floating well structure to eliminate the threshold voltage drop and the body effect problems. Due to the new circuit scheme, the new charge pump circuit can be used in a conventional n-well CMOS process for low supply voltage (2 V to 0.9 V) and have high charge pump gain and efficiency. The proposed circuit is based on the 0.25 μm CMOS technology, and the clock frequency is 50 MHz.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003

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