Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design

Global on-chip interconnect technology will become the limiting factor for the design of future deep submicron (DSM) SoC. DSM effects, inherent to long interconnects such as unpredictable, large wire delays and non-negligible bit error rates resulting from noise and crosstalk as well as the synchronization between modules with autonomous clock supplies need to be addressed using appropriate on-chip communication schemes. A possible solution is the employment of high-performance single/double wire, packet-oriented, error-concealing communication protocols for on-chip communication. In this paper we propose an efficient design methodology for packet-oriented SoC communication in a SystemC-based design flow. The methodology is based on high level specification, incremental refinement and simulation of a communication protocol in the system context using an extension to SystemC, which follows a high-level synthesis of all interacting protocol controllers in an on-chip network from the initial protocol specification. The methodology was used for implementation of the USB 2.0 protocol for an on-chip communication network.