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The trial-and-error approach still dominates on-chip electrostatic discharge (ESD) protection circuit design. We present a new predictive mixed-mode ESD protection simulation-design methodology, which involves multiple-level electro-thermal-process-device-circuit-layout coupling in an ESD protection simulation that solves complex electro-thermal equations self-consistently at process, device and circuit levels, in a coupled fashion. In this way, we can investigate ESD protection circuit behavior without any pre-assumption. Practical design examples in commercial 0.35 μm CMOS are presented.