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A media processor supporting MPEG-4 SP@L3 and H.263 baseline has been eveloped. This chip includes a RISC core, dedicated video accelerator, audio/voice CODEC, pre/post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, a configurable bus architecture that may optimize the bus transaction overhead was adopted. Not only dedicated coprocessors for the acceleration of multimedia processing but also some novel techniques such as zero vector skip, DCT reduction, and localized isolation of functional blocks were implemented for the application specific performance tuning. Enhanced error resilience was also implemented for error-prone environment, and additional innovative low-power design techniques were applied for portable applications. This processor contains 2M gates on 56mm2 die using of 0.18um CMOS HLM technology.