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Dual clock rate block data parallel architecture [multiprocessor based FIR filter example]

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2 Author(s)
An-Te Deng ; Signal Process. Lab., North Carolina State Univ., Raleigh, NC, USA ; W. E. Alexander

This paper presents a multiprocessor system with a dual clock rate. We used the block data overlap-save algorithm and the block data parallel architecture (BDPA) to implement a two dimensional (2D) FIR filter. We were able to significantly improve the performance of the block data parallel architecture (BDPA) multiprocessor system by using a dual rate clock as compared to the performance using a single rate clock. We designed a 2D-FIR filter system with a four processor module array to demonstrate the improvement in performance. It had a throughput performance of 7.975 samples per processor clock cycle and the processor utilization was 78.53%.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:4 )

Date of Conference:

25-28 May 2003