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This paper deals with the FPGA-implementation of quadrature direct digital frequency synthesizers (QDDFS), and in particular with those based on CORDIC, interpolation and memory compression. We provide results of maximum throughput, i.e. 302 MHz, when mapping QDDFS architectures on current LUT-based field-programmable technology. We take into account those VLSI design guidelines that work well on FPGAs and architectural considerations to design efficient (in terms of area and throughput) QDDFS, up to 56% faster than commercial cores. Finally, we present a design map that combines the phase-to-amplitude techniques reviewed in this article so as to minimize the overall area.