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Efficient bit-serial systolic array for division over GF(2m) [elliptic curve cryptosystem applications]

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4 Author(s)
Chang Hoon Kim ; Dept. of Comput. & Inf. Eng., Daegu Univ., Kyungbuk, South Korea ; Soonhak Kwon ; Chun Pyo Hong ; In Gil Nam

In this paper, we propose a new bit-serial systolic array for computing division over GF(2m) using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2m). Analysis shows that the proposed array provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic arrays with the same I/O format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuits of elliptic curve cryptosystems (ECC).

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:2 )

Date of Conference:

25-28 May 2003