Clock recovery circuit with adiabatic technology (quasi-static CMOS logic)

This paper presents a novel approach of using digital adiabatic circuit to perform clock-recovery for an amplitude-shift-key (ASK) transmission system. The adiabatic clock recovery consists of only 39 stages of AqsCMOS inverter and consumes 106 /spl mu/W. The circuit is specially designed for low power contactless smart card using adiabatic logic.