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Clock recovery circuit with adiabatic technology (quasi-static CMOS logic)

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4 Author(s)
W. K. Yeung ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China ; Cheong-Fat Chan ; Chiu-Sing Choy ; Kong-Pang Pun

This paper presents a novel approach of using digital adiabatic circuit to perform clock-recovery for an amplitude-shift-key (ASK) transmission system. The adiabatic clock recovery consists of only 39 stages of AqsCMOS inverter and consumes 106 μW. The circuit is specially designed for low power contactless smart card using adiabatic logic.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:2 )

Date of Conference:

25-28 May 2003