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This paper proposes a DFE (Decision Feedback Equalizer) equalizer with an error feedback filter using the Multi-Modulus Algorithm (MMA). The proposed equalizer has been designed for 64/256 QAM constellations. The existing MMA equalizer uses two transversal filters or feedforward and feedback filters, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The architecture has been modeled by VHDL and logic synthesis has been performed using the 0.25 μm Faraday CMOS standard cell library. The total number of the gates is about 190,000 gates. The proposed equalizer operates at 15 MHz and provides a symbol rate up to 64 Mbps which is higher than the DOCSIS recommendation.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:4 )
Date of Conference: 25-28 May 2003