Referenced Items are not available for this document.
In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the proposing parallel turbo decoder with 4 SISO's and a dividable S-random interleaver with 0.35 μm CMOS technology, which occupies 21.6 mm2, supports up to 41.8 Mb/s decoding rate.
Published in:
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
(Volume:2
)
Date of Conference: 25-28 May 2003
- Page(s):
- II-65 - II-68 vol.2
- Print ISBN:
- 0-7803-7761-3
- INSPEC Accession Number:
- 7749847
- Digital Object Identifier :
- 10.1109/ISCAS.2003.1205889
- Product Type:
- Conference Publications
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