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We present a 200 MHz 6 bit analog-to-digital converter (ADC) with folding and interpolation, designed in a 0.35μm CMOS technology. The ADC makes use of a new folding circuit with fully-differential input and with large bandwidth and gain. The interpolation is realized in current-mode, allowing the use of a 2.5 V supply voltage. It is shown that a Wallace-tree encoder can be used to convert the circular to binary code, which is an efficient solution for medium resolution ADCs. The ADC is implemented in 0.26 mm2, and has a power consumption of 78.8 mW, which is lower than that of alternative realizations for this frequency range.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:1 )
Date of Conference: 25-28 May 2003