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A power-efficient architecture for high-speed D/A converters

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2 Author(s)
Farzan, K. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Johns, D.A.

A novel power-efficient architecture for high-speed D/A converters is proposed. A data look ahead technique is used to pre-switch the current sources so that the DAC current is reduced when generating small voltage levels. Interestingly, this technique also eliminates the need for a pre-driver block for each current-cell, which also saves power. Based on this architecture, a 6-bit DAC is designed in 0.18μm standard digital CMOS technology. The update rate for this DAC is 1GS/s and it consumes only 24mW at 1GS/s.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:1 )

Date of Conference:

25-28 May 2003