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A CMOS 8-bit, 33.3MS/s flash ADC with ±1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than ±0.3LSB. Signal-to-(noise and distortion) ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with ±1.5V power supply.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:1 )
Date of Conference: 25-28 May 2003