By Topic

Design techniques for a fully differential low voltage low-power flash analog to-digital converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Tsung-Sum Lee ; Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Li-Dyi Luo ; Chin-Sheng Lin

A CMOS 8-bit, 33.3MS/s flash ADC with ±1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than ±0.3LSB. Signal-to-(noise and distortion) ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with ±1.5V power supply.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:1 )

Date of Conference:

25-28 May 2003