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In this paper, a new pixel structure for a CMOS imager, called the shared-zero-buffer pseudo-active-pixel-sensor (SBPAPS), is proposed and analyzed. It has the advantages of low dark current and high signal-to-noise ratio (S/N) over the conventional active-pixel-sensor (APS) imager. It also has a higher frame rate as compared with the pseudo-active-pixel-sensor (PAPS) imager. The shared-zero-buffer structure is proposed to suppress both the photodiode dark current and the leakage current of the pixel switches by keeping both biases of photodiode and parasitic pn junction in the pixel at zero or near zero voltage. The improved double delta sampling (DDS) circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed SBPAPS CMOS imager with a format of 352×288 (CIF) has been fabricated by using a 0.25 μm single-poly-five-level-metal (1P5M) N-well CMOS process. The proposed CMOS imager has a fill factor of 42%, chip size of 3000 μm×2800 μm, and dc power dissipation below 30 mW under a power supply of 3.3 V. It can be applied in the design of low-dark-current CMOS imager systems.