Skip to Main Content
In this paper we present a novel noise optimization design technique using voltage boosting for low-noise amplifiers (LNAs). High performance FET LNAs use inductive source degeneration to generate the real part of the input impedance without using a noisy resistor. Normally the source inductance is adjusted to meet the 50 Ω power matching condition. In this paper we show that if the source degenerating inductance value is adjusted such that the impedance is larger than the source resistance, the output noise power can be reduced. The maximum input resistance is limited by the quality factor of the gate inductor and transconductance saturation at high gate bias voltage due to short channel effects. An appropriate input resistance and device geometry can be selected to optimize the NF. The tradeoff between noise figure and linearity has also been considered. To verify our design concepts a prototype MESFET LNA with 1.65-dB noise figure and 5.2-dBm third order input intercept point has been designed and tested. It consumes 12mW from a 2.0-V power supply.