A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18 /spl mu/m CMOS process

A 10-bit low power track-and-hold (T/H) circuit aimed at the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T/H is sampling at 80 MS/s, has a 30 MHz analog bandwidth and is designed in a 0.18 /spl mu/m CMOS process with a supply voltage of 1.8 V. A switched capacitor topology incorporating correlated double sampling is used for the T/H circuit and the amplifier is a folded cascode operational transconductance amplifier (OTA) with gain boosting. In this paper, the design of the complete T/H is described, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.