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VLSI architecture for motion vector quantization

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4 Author(s)
Wen-Jyi Hwang ; Inst. of Comput. Sci. & Inf. Eng., Nat. Taiwan Normal Univ., Taipei, Taiwan ; Chien-Min Ou ; Wen-Ming Lu ; Chun-Fu Lin

The paper present a novel VLSI architecture for block-matching operations based on motion vector quantizers (MVQs). Since the distribution of the MVQ check point locations is irregular, the usual VLSI architectures for regular block-matching processes may not be effective for the hardware implementation of the MVQ. Our architecture solves this problem by adopting a scheme capable of performing both sequential and parallel block-matching processes. For check points having close locations, their block-matching processes are performed sequentially to reduce both the I/O rate and the clock cycle. On the other hand, we perform the parallel block-matching processes for checkpoints which are widely separated so that the clock cycle can be reduced while retaining the I/O rate. Because of the flexibility for sequential and parallel selection, our architecture requires less clock cycle and I/O rate for the MVQ hardware implementation as compared with other existing architectures.

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Consumer Electronics, IEEE Transactions on  (Volume:49 ,  Issue: 1 )