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Damage-free SiO2/SiNx side-wall gate process and its application to 40 nm InGaAs/InAlAs HEMT's with 65% InGaAs channel

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4 Author(s)
Dae-Hyun Kim ; Sch. of Electr. & Comput. Eng., Seoul Nat. Univ., South Korea ; Suk-Jin Kim ; Young-Ho Kim ; Kwang-Seok Seo

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO2 and SiNx dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40 GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100 nm range.

Published in:

Indium Phosphide and Related Materials, 2003. International Conference on

Date of Conference:

12-16 May 2003