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Developing a teaching environment for rapid design and verification of complex digital/computing systems

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4 Author(s)
D. Hung ; Dept. of Comput. Eng., San Jose State Univ., CA, USA ; J. Vien ; W. Chan ; Chi-wei Fu

This paper first discusses the need and difficulties for the education community to establish an environment to teach system-level design and verification, then describes the activities at San Jose State University (Computer Engineering Department) in developing such an environment through a low cost approach. A demo is provided along with the paper.

Published in:

Microelectronic Systems Education, 2003. Proceedings. 2003 IEEE International Conference on

Date of Conference:

1-2 June 2003