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This work presents a software framework for rapid behavioral modeling and simulation of analog-to-digital converters (ADCs). The framework is based on the SystemC C++ class libraries and has proven to be an effective tool for exploring different system-level architectures in the early stages of the design process. Post-processing analysis tools are included for static and dynamic performance calculation. To compare the performance of our SystemC framework with Verilog, a 12 bit pipelined ADC is modeled and simulated, and we report on the results of the comparison.