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Recent efforts to add new services to the Internet have increased the interest in designing flexible routers that are easy to extend and evolve. This paper describes a new hardware architecture based on dynamic reconfigurable logic (DRL) for high throughput networking applications. It mainly focuses on content-based router and on how to schedule efficiently its computation time. This scheduling task is difficult because of the various features of the underlying hardware such as multicontext, control-data path architecture and memory interface. Experimental results show some improvements over most recent network processors as well as a better hardware synthesis methodology.