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The missing kink to seamless simulation [nanometer CMOS ULSI]

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1 Author(s)
Xing Zhou ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

This paper reviews the trends and needs in multilevel modeling in the context of nanometer CMOS ULSI systems, with an emphasis from the model/tool developer's perspective. A dual representation of the transistors/circuit is proposed and demonstrated through physics-based compact modeling and a single-engine circuit simulator based on subcircuit expansion. Extension to process correlation and block-level representation is also proposed, which will be the key to studying process effects on system performance. This consistent dual representation allows detailed physics captured at a lower level to be propagated to the higher level of abstraction. The key idea is to build a physics-based device compact model (CM) based on technology characterization, which serves as the building block for an implicit multilevel circuit simulator based on a subcircuit-expansion approach. In this way, process variation can be captured through device CMs, and its effects on circuit/system performance can be linked to a consistent hierarchy of abstractions within the same simulator engine.

Published in:

Circuits and Devices Magazine, IEEE  (Volume:19 ,  Issue: 3 )