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Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue

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5 Author(s)
Blecker, E.B. ; Univ. of California, Davis, CA, USA ; McDonald, T.M. ; Erdogan, O.E. ; Hurst, P.J.
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An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter. To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio is 45 dB, and the spurious-free dynamic range is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm2.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 6 )

Date of Publication:

June 2003

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