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A mixed-mode ESD protection circuit simulation-design methodology

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8 Author(s)
Haigang Feng ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Guang Chen ; Rouying Zhan ; Qiong Wu
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On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-μm CMOS and BiCMOS processes, are presented.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 6 )

Date of Publication:

June 2003

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