A high-performance architecture and BDD-based synthesis methodology for packet classification

Packet classification is a computationally intensive task that routers need to perform in order to implement basic functions such as next-hop lookup, as well as advanced features such as quality of service and security. Formally, a classifier examines each incoming packet, and determines which rules to apply to it. Semantically, the classifier is characterized by a function mapping the packet header to an integer encoding the action to be taken for that packet. The function itself is syntactically presented as a chain of if-then-else statements. Since the header consists of a fixed number of bits, it is natural to use logic synthesis to implement fast small classifiers in hardware. When doing this, there are two key issues that must be kept in mind: 1) these functions change over time, so the target architecture needs to be reconfigurable and 2) classification functions have a structure which should be exploited. We show that Internet Protocol forwarding, which is a special case of classification, can be performed by provably small circuits at very high speed by mapping the binary decision diagram (BDD) representation of the classification function to a cascaded array of lookup tables. This approach does not immediately carry over to general packet classification; the BDD for the classification function grows very large. We develop a solution based on partitioning to overcome this problem. We prove NP-completeness of optimal partitioning. We describe a heuristic for partition. The latency introduced by pipelining can be reduced by partially collapsing the BDD. We present an efficient algorithm based on dynamic programming to obtain an optimum grouping of variables that minimizes the total amount of memory required for a given number of levels.