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Metal gate and high-k integration for advanced CMOS devices

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18 Author(s)
Guillaumot, B. ; STMicroelectronics, Crolles, France ; Garros, X. ; Lime, F. ; Oshima, K.
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An advanced CMOS process has been proposed which include key features : 75 nm gate length, damascene metal gate, high-k dielectrics with 1.35 nm equivalent oxide thickness (EOT). Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface Low gate current and low subthreshold slope make it attractive for low stand by power application.

Published in:

Plasma- and Process-Induced Damage, 2003 8th International Symposium

Date of Conference:

24-25 April 2003