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Design methodology for construction of asynchronous pipelines with Handel-C

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3 Author(s)
Self, R.P. ; Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK ; Fleury, M. ; Downton, A.C.

CSP (communicating sequential processes) channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an exemplar, pipelined design of the Karhunen-Loeve transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs.

Published in:

Software, IEE Proceedings -  (Volume:150 ,  Issue: 1 )

Date of Publication:

Feb. 2003

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