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We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high off-chip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses. While synchronous transceivers commonly use multi-phase clocks to control the data multiplexing and demultiplexing, our clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry. Furthermore, our clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. Our SPICE simulations report that in a 0.18-μm CMOS technology this transceiver design operates at up to 3-Gb/s and dissipates 77 mW of power with a 1.8-V supply voltage.
Date of Conference: 12-15 May 2003