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The continued down-scaling of DRAM cell size is required while maintaining a sufficiently high storage capacitance per cell (>25 fF/cell). Before introducing high K dielectrics, optimization of the ON (Oxide-Nitride) stack using hemispherical-grained (HSG) polysilicon for the bottom electrode is analyzed in detail. First of all, it is necessary to identify the failure modes relevant to such cell stacks. Capacitance and current stability under temperature and electrical stress are demonstrated to be not critical for the 0.13 μm CMOS technology under investigation. On the contrary, soft breakdown events limit the cell lifetime. By knowing the critical parameters, we demonstrate that oxidation step suppression enables us to find good candidates considering capacitance, leakage current and reliability.
Date of Conference: 30 March-4 April 2003