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Power constrained test scheduling with dynamically varied TAM

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2 Author(s)
Dan Zhao ; Dept. of Comput. Sci. & Eng., State Univ. of New York, USA ; S. Upadhyaya

In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.

Published in:

VLSI Test Symposium, 2003. Proceedings. 21st

Date of Conference:

27 April-1 May 2003