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An ASIC implementation of adaptive arithmetic coding

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4 Author(s)
G. Acunto ; Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland ; M. Sans ; A. Burg ; W. Fichtner

We present an improved version of an ASIC implementation of the adaptive arithmetic coding algorithm which uses a two-level memory hierarchy. We propose algorithmic modifications and a special hardware structure to speed-up the design without degrading the compression ratio obtained using this memory hierarchy. Moreover, several new features which increase the compression efficiency are introduced. Finally, a VLSI implementation based on the results of our work is presented.

Published in:

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on  (Volume:2 )

Date of Conference:

3-6 Nov. 2002