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An FPGA implementation of a flexible architecture for H.263 video coding

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4 Author(s)
Garrido, M.J. ; Univ. Politecnica de Madrid, Spain ; Sanz, C. ; Jimenez, M. ; Menesses, J.M.

The architecture and design of MVIP-2, a flexible and efficient proposal for implementing an H.263 video coder, is explained in this paper. The MVIP-2 architecture consists of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The MVIP-2 design has been written in synthesizable hardware description language (HDL) and fully tested with hardware-software co-simulation using standard video sequences. Finally, MVIP-2 has been prototyped onto a system based on an FPGA and a RISC.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:48 ,  Issue: 4 )

Date of Publication:

Nov 2002

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