By Topic

High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Taegeun Park ; Comput. & Electron. Eng., Catholic Univ. of Korea, Bucheon, South Korea ; Sunkyung Jung

This paper presents an efficient lattice structure based VLSI architecture of 2D discrete wavelet transform (DWT) for hierarchical image compression, which is scalable to extend to an arbitrary 2D DWT with M laps and J levels. The proposed architecture consists Of four 1D lattice filters, which processes in horizontal and vertical directions at the same time. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N2/2 to compute an N×N image because the even and odd rows are processed simultaneously. Compared to conventional approaches, the proposed architecture shows shorter period to complete 2D DWT while requiring relatively less hardware resources. Therefore, the proposed architecture can be applied in real-time video signal processing such as JPEG-2000 and MPEG4, which require high speed processing. The process schedule using the data dependency graph, performance, and the required hardware cost are discussed.

Published in:

IEEE Transactions on Consumer Electronics  (Volume:48 ,  Issue: 4 )