Referenced Items are not available for this document.
A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-μm CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:38
,
Issue:
5
)
Date of Publication: May 2003
- Page(s):
- 782 - 792
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7608821
- Digital Object Identifier :
- 10.1109/JSSC.2003.810052
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 29 April 2003
- Issue Date :
- May 2003
- Sponsored by :
- IEEE Solid-State Circuits Society
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