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A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

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5 Author(s)
Hyde, J. ; Impinj Inc., Seattle, WA, USA ; Humes, T. ; Diorio, C. ; Thomas, M.
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Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-μm CMOS logic processes. We trim the static integral nonlinearity to ±0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm2 of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 5 )