Referenced Items are not available for this document.
Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-μm CMOS logic processes. We trim the static integral nonlinearity to ±0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm2 of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:38
,
Issue:
5
)
Date of Publication: May 2003
- Page(s):
- 734 - 740
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7608814
- Digital Object Identifier :
- 10.1109/JSSC.2003.810049
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 29 April 2003
- Issue Date :
- May 2003
- Sponsored by :
- IEEE Solid-State Circuits Society
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