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A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

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8 Author(s)
Fujibayashi, M. ; Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan ; Nozawa, T. ; Nakayama, T. ; Mochizuki, K.
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A still-image encoder based on vector quantization (VQ) has been developed using 0.35-μm triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600×2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.

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Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 5 )