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A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

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4 Author(s)
Mathew, S. ; Circuit Res. Labs., Intel Corp., Hillsboro, OR, USA ; Anders, M. ; Krishnamurthy, R.K. ; Borkar, S.

This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-VT semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 5 )