By Topic

A compact analytical model for asymmetric single-electron tunneling transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Inokawa, H. ; NTT Basic Res. Labs., NTT Corp., Kanagawa, Japan ; Takahashi, Yasuo

Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into account, and is therefore very simple. Even so, it can accurately reproduce the peculiar behaviors of an asymmetric SETT, such as the skew in the drain current-gate voltage characteristics and the Coulomb staircase in the drain current-drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SETT are also derived according to the same scheme, and it is demonstrated that the model can precisely describe the various aspects of the SETT behavior.

Published in:

Electron Devices, IEEE Transactions on  (Volume:50 ,  Issue: 2 )