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Low-voltage low-power nonvolatile floating-gate memory device operation can be achieved by using alternative tunnel barriers consisting of at least two dielectric layers with different dielectric constants k. Low-k/high-k (asymmetric) and low-k/high-k/low-k (symmetric) barriers enable steeper tunneling current-voltage characteristics. Their implementation is possible with high-k dielectric materials that are currently investigated for SiO/sub 2/ replacement in sub-100-nm CMOS technologies. We show that a reduction in programming voltages of up to 50% can be achieved. This would significantly reduce the circuitry required to generate the high voltages on a nonvolatile memory chip, while maintaining sufficient performance and reliability.