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The AE64000 is a 64 bit embedded processor targeting high-end embedded applications such as HDTV, DVD, and 3D graphics. To achieve a higher performance for the AE64000, we design a branch predictor for the processor, and find the optimum parameters for the design through cycle-accurate simulations on SpecINT benchmarks and embedded applications (Dhrystone and Whetstone). In the AE64000, branch prediction is complicated by the instruction folding unit (IFU) of the processor front-end. By predicting on a pre-PC in the IFU, rather than using a PC in the pipeline core, we can effectively eliminate the branch misprediction penalty on a correct prediction. We have developed the AE64000 simulator to evaluate the performance of the designed branch predictor, and selected the optimum branch predictor configuration by considering cost-effectiveness as well as by analyzing the results generated from the AE64000 simulator. The selected branch predictor has been implemented in Verilog and is added to AE64000 pipeline.
Date of Conference: 21-24 Jan. 2003