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A low power CMOS circuit with variable source scheme (VSCMOS)

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2 Author(s)
Yasuda, T. ; Semicond. Technol. Dev. Eng. & Technol. Service, IBM Japan, Shiga, Japan ; Hosokawa, K.

This paper proposes a method to reduce the standby leakage current of MOSFET by controlling the voltage of the source node. The method allows the use of a low threshold device for high performance speed and low power dissipation in both active and standby periods. This method can be easily applied for conventional ASIC library circuits because no additional processes, circuits, or devices except slight modification for the body contact cell are required.

Published in:

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Date of Conference:

21-24 Jan. 2003