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A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints

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1 Author(s)
S. Tayu ; Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan

The module placement is one of the most important problems in VLSI design. A practical VLSI placement problem often includes some constraints. In this paper, we propose a penalty function approach for the efficient simulated annealing search on the solution space of constrained problems. We apply the penalty function approach to the placement problem with boundary constraints. Experimental results show that our proposed method can accomplish more effective simulated annealing search than the conventional method proposed for two module sets, an MCNC benchmark ami49 and a randomly generated module set.

Published in:

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Date of Conference:

21-24 Jan. 2003