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Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling

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6 Author(s)
Won-Seok Lee ; Dept. of Device Solution Network, Samsung Electron. Co. Ltd., South Korea ; Keun-Ho Lee ; Jin-Kyu Park ; Tae-Kyung Kim
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In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property of the effective permittivity in the modeled geometry is examined. Validation with the realistic 3D structures clearly demonstrates the importance and correctness of the geometry modeling.

Published in:

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Date of Conference:

24-26 March 2003