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Using integer equations for high level formal verification property checking

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2 Author(s)
Alizadeh, B. ; Electr. & Comput. Eng., Tehran Univ., Iran ; Kakoee, M.R.

This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verification methods use BDDs, as a low level representation of a design. BDD operations require separation of data and control parts of a design and their implementation requires large CPU time and memory. In our method; a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. This reduces the need for large BDD data structures and uses far less memory. Furthermore, this method is applied to circuits without having to separate their data and control sections. Integer equations are solved recursively by replacement and simplification operations. For this implementation, we use a canonical form of integer equations. This paper compares our results with those of the VIS verification tool that is a BDD based program.

Published in:

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Date of Conference:

24-26 March 2003