Rapid reduction of gate-level electrical defectivity using voltage contrast test structures

Voltage contrast test structures for use with KLA-Tencor's /spl mu/Loop/spl trade/ system have been developed for rapid reduction of the yield limiting defect density (D0) from the gate module. The gate module is typically one of the top three sources of random yield loss in advanced integrated circuit technologies. The /spl mu/Loop system allows in-line detection of nearly 100% of the killer defects affecting these special comb test structures, which mimic product. Because this system is based on in-line voltage contrast inspection, experiments may be completed extremely rapidly. These two advantages make this system a major improvement over past techniques for debugging the gate module. Implementation of gate-level /spl mu/Loop test structures is challenging because of the lack of a direct ground path from the polysilicon used to make the gate. This paper describes how this challenge is overcome. Application of this methodology to a recent technology at Agere Systems is described. Ten experimental lots were used over a period of three quarters to drive gate-level D0 reduction. Over this period, the gate-level D0 decreased by 62%.