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Evaluation of final test process in 64-Mbit DRAM manufacturing system through simulation analysis

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3 Author(s)
K. Nakamae ; Dept. of Inf. Syst. Eng., Osaka Univ., Japan ; H. Ikeda ; H. Fujioka

We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an event-driven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMS and SDRAMs are considered. The overall number of planned production chips during a month is 3 million. The number of chips simultaneously tested is 32, 64, 128, and 256. Simulations for six months were carried out as a function of number of memory test systems by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI

Date of Conference:

31 March-1 April 2003